1. Field of the Invention
The invention relates to a MOS semiconductor device and a method of fabricating the same.
2. Description of the Related Art
With higher integration and smaller size in a MOS semiconductor device, a problem of degradation of a device due to hot carriers has become significant, resulting in reduction in reliability. To solve this problem, there is widely used LDD (Lightly Doped Drain) structure which lightens an electric field formed between a drain diffusion layer and a gate electrode to thereby suppress generation of hot carriers.
A conventional method of fabricating a MOS semiconductor device is explained hereinbelow with reference to FIGS. 1A to 1E.
First, as illustrated in FIG. 1A, a p-type single crystal silicon substrate 1 is thermally oxidized to thereby form a gate oxide layer 2 at a surface of the silicon substrate 1. Then, for the purpose of adjusting a threshold voltage, the silicon substrate 1 is ion-implanted at about 10 to about 30 keV with doses of about 1.times.10.sup.11 to about 1.times.10.sup.13 cm.sup.-2 boron to thereby form a p-type impurity diffusion layer 3 in the silicon substrate 1.
Then, as illustrated in FIG. 1B, a gate electrode 4 is formed on the gate oxide layer 2 by chemical vapor deposition (CVD) and photolithography. The gate electrode 4 is made of polysilicon. As an alternative, the gate electrode 4 may be made of amorphous silicon. Then, the silicon substrate 1 is ion-implanted at about 30 to about 70 keV with doses of about 1.times.10.sup.13 to about 1.times.10.sup.14 cm.sup.-2 phosphorus with the gate electrode 4 being used as a mask, to thereby form n-type impurity diffusion layers 5 in the silicon substrate 1. The thus formed n-type impurity diffusion layers 5 have LDD structure.
Then, as illustrated in FIG. 1C, a silicon dioxide layer (not illustrated) is deposited all over the silicon substrate and the gate electrode 4 by CVD. Then, the silicon dioxide layer is etched back by anisotropic etching. As a result, the silicon dioxide layer remains as a sidewall oxide layer 6 on a sidewall of the gate electrode 4.
Then, the silicon substrate 1 is ion-implanted at about 50 to about 70 keV with doses of about 1.times.10.sup.14 to about 1.times.10.sup.16 cm.sup.-2 arsenic with the gate electrode 4 and the sidewall oxide layer 6 being used as a mask, to thereby form LDD-structured n+type impurity diffusion layers 7 in the silicon substrate 1, followed by annealing for activating the n-type impurity diffusion layers 5 and the n+type impurity diffusion layers 7. The n-type impurity diffusion layers 5 and the n+type impurity diffusion layers 7 act as source/drain regions.
Then, as illustrated in FIG. 1D, an interlayer oxide layer 8 is formed over the sidewall oxide layer 6 and the gate electrode 4 by CVD by a thickness in the range of about 1000 to about 2000 angstroms.
Then, as illustrated in FIG. 1E, there is formed an interlayer insulating layer 9 on the interlayer oxide layer 8 by a thickness in the range of about 5000 to 8000 angstroms, followed by annealing for reflowing. The interlayer insulating layer 9 is made of borophosphosilicate glass. Then, there are formed contact holes 10 at predetermined locations throughout the interlayer insulating layer 9 and the interlayer oxide layer 8. Then, metal wiring layers 11 are formed filling the contact holes 10 therewith. Thus, there is completed a MOS semiconductor substrate.
The LDD-structured MOS semiconductor device illustrated in FIGS. 1A to 1E has a problem that if the gate oxide layer 2 were formed thinner, a device would be degraded by hot carriers with the result of reduction in reliability. This is because moisture or hydroxyl (OH) groups contained in the interlayer insulating layer 9 diffuse into source/drain regions and/or the gate oxide layer 2 through the interlayer oxide layer 8 situated just above the gate electrode 4.
Katsuyuki Machida et al. have suggested "Improvement of Water-related Hot-carrier Reliability by using ECR Plasma-SiO.sub.2 " in IEEE Transactions on Electron Devices, Vol. 41, No. 5, May 1994, pp. 709-714. According to the study, water-related hot-carrier degradation is reduced by using ECR plasma SiO.sub.2 as the water-blocking layer under the water-containing films such as SOG or TEOS-0.sub.3. The water-blocking mechanism proposed therein is, based on the reaction between Si--H bonds and H.sub.2 O in ECR-SiO.sub.2 film.